* * * * * c-mos rll 1-7 decoder (gate array) ?op view 1 10 20 30 40 44 45 50 60 70 80 88 89 90 100 110 120 130 132 133 140 150 160 170 176 v dd 13 v ss 23 v ss v dd 13 v ss t v ss v dd 13 v ss v ss v dd 13 v ss v ss v ss 23 v dd 13 v ss v ss v dd 13 v ss 23 v ss v ss v dd 13 v ss v ss t v dd 13 v ss v ss 23 v dd = +5v v ss = gnd CXD8940BQ (1/3) il16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 pin no. i/o signal i i i i i i i i i i i i i i i i i i o o o o o o o o o i i i i i i i i i i o o a17i a3i a2i a1i cs1i cs2i cs3i cs5i cs6i dpwaiti rdi v dd 13 wrli wrhi reseti moniseli v ss 23 crc formi ampatti sm seli v ss ramcso piocso dspncso dsptcso pio2cso dawro waito cs2sp1o cs2sp2o trt unlocki trn unlocki v dd 13 tcnt ti tcnt ni pup ti pup ni holdi ti v ss t holdi ni dsn rdi dsn csi trvdirno teplso no pin no. i/o signal pin no. i/o signal pin no. i/o signal 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 o o o o o o o o o o o o o o o o o o o i i o o o o o o o o o o o o o o o o o piplso no teplso to piplso to dsnd0o dsnd1o dsnd2o v ss dsnd3o dsnd4o dsnd5o dsnd6o v dd 13 dsnd7o dsnd8o dsnd9o dsnd10o v ss dsnd11o dsnd12o dsnd13o dsnd14o dsnd15o dst rdi dst csi trvdirto dstd0o dstd1o dstd2o v ss dstd3o dstd4o dstd5o v dd 13 dstd6o dstd7o dstd8o dstd9o dstd10o v ss dstd11o dstd12o dstd13o dstd14o dstd15o 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 i i i i i o o o o o o o o o o o o o o o o o o o o o o o o o o o i i i i v ss rdat 1ni rclk 1ni smark 1ni v ss 23 sen 1i refn cki rdat0 1no rdat1 1no msel0 1no msel1 1no v dd 13 bsh 1no psh 1no rsh 1no eqs 1no v ss dbias 1no dpeak 1no sm 1no ren 1no wst 1no crcerr no dclk 1no crcdatamo syndetmo v ss rsdetmo qadrdatmo amdetmo sec endmo syrs detmo v dd 13 reenmo smcclrmo amwinmo synwinmo dareamo v ss 23 v ss reft cki rdat 1ti rclk 1ti smark 1ti 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 o o o o o o o o o o o o o o o i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i i i i rdat0 1to rdat1 1to msel0 1to msel1 1to bsh 1to psh 1to v ss rsh 1to eqs 1to dbias 1to dpeak 1to v dd 13 sm 1to ren 1to wst 1to crcerr to v ss dclk 1to testi test2i d0io d1io d2io d3io d4io d5io d6io d7io v ss t d8io d9io d10io v dd 13 d11io d12io d13io d14io d15io v ss clk20mw clk20m a19i a18i v ss 23 CXD8940BQ (2/3) v dd = +5v v ss = gnd
address mark detect result address mark detect window bias loop sample hold crcc detect result crcc error signal chip select data bus valid data area wait control bias loop test enable clock shnchronized to rdat0 and rdat1 peak loop test enabel data bus eq start signal rf mode select clock pulse for traverse counter peak loop sample hold rdat latch by rclk nrzi and rll convert sector read enable data read enable resync detect result read sample hold sector end detect result sector mark regenerate clear signal by sector mark sync detect result sync and resync or between detect and auto correct sync detect window traverse counter count direction write start input a1i~3i a17i~9i ampatti clk20mi clk20mwi crc formi cs1i~6i dpwaiti dsn csi, dsn rdi, dst csi, dst rdi holdi ni, holdi ti moniseli pup ni, pup ti, tcnt ni, tcnt ti rclk 1ni, rclk 1ti rdat 1ni, rdat 1ti rdi refn cki, reft cki reseti sen 1i sm seli smark 1ni, smark 1ti test trn unlocki, trt unlocki wrhi, wrli address bus address bus address mark pattern control 20 mhz clock window pulse generator master clock crcc pattern detect control for track and sector chip select chip select wait traverse counter read control from dsp traverse counter hold mode monitor output signal select clock pulse input for traverse counter clock synchronized to rdat (ttl input) disk data playback (ttl input) from rf data bus read referense clock (same frequency as rclk) system reset data read enable window pulse decode select sector mark detect test pin tracking error acknowledge data bus write ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; output amdeto amwinmo bsh ino, bsh 1to crcdatamo crcerr no, crcerr to cs2sp1o, cs2sp2o, dspncso, dsptcso, pi0cso, pi02cso, ramcso d0io~d15io dareamo dawro, waito dbias 1no, dbias ito dclk 1no, dclk 1to dpeak 1no, dpeak 1to dsnd0o~dsnd15o, dstdo~dstd15o eqs 1no, eqs 1to msel0 1no, msel0 1to, msel1 1no, msel1 1to piplso no, pipls0 to, teplso no, tepls0 to psh 1no, psh 1to qadrdatmo rdat0 1no, rdat0 ito, rdat1 1no, rdat1 1to reenmo ren 1no, ren 1to rsdetmo rsh 1no, rsh 1to sec endmo sm 1no, sm 1to smcclrmo syndetmo syrs detmo synwinmo trvdirno,trvdirto wst 1no, wst 1to ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CXD8940BQ (3/3)
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